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Combining architecture exploration and a path to implementation to build a complete SoC design flow from system specification to RTL

Auteur(s) : F. Samet, W. Cesario, A. Dziri, F.R. Wagner, A. A. Jerraya

ISRN: TIMA-RR--02/11-01--FR

This paper presents a full System-on-Chip (SoC) design flow from system specification to RT-level. A new approach to obtain a full path to implementation for SoC design is proposed. This approach combines architecture design space exploration using the VCC design environment and system synthesis using the ROSES design flow, allowing a true and complete system level design flow. The experiment with a VDSL application shows a significant reduction of design time.