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Efficient Fault Dectection Architecture Design of Latch-based Low Power DSP/MCU Processor

Auteur(s) : H. Yu, M. Nicolaidis, L. Anghel, N.-E. Zergainoh

ISRN: TIMA-RR--2011/01--FR

Soft errors is an important emerging concern in the design and implementation of future complex VLSI designs, like DSP and microprocessors. In this paper, we present an efficient approach, based on improved time redundancy and latch-based design techniques to detect single-event upsets (SEUs), single event transients (SETs) and timing/delay faults. A complex low power DSP/MCU processor is used to evaluate the SETs detection efficiency in 65nm and 45nm technologies. The results of the fault injection experiments show that GRAAL has significant error detection efficiency and relatively lower area and power consumption overhead with negligible performance degradation.