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Estimation of test metrics for the optimisation of analogue circuit testing

Auteur(s) : A. Bounceur, E. Simeu, S. Mir, L. Rolindez

ISRN: TIMA-RR--06/10-03--FR

The estimation of test metrics such as defect level, test yield or yield loss is important in order to quantify the quality and cost of a test approach. For design-for-test purposes (DFT), this is important in order to select the best test measurements but this must be done at the design stage, before production test data is made available. In the analogue domain, previous works have considered the estimation of these metrics for the case of single faults, either catastrophic or parametric. The consideration of single parametric faults is sensible for a production test techniquesif the design is robust. Howewer, in the case that production test limits are tight, test escapes resulting from multiple parametric deviations may become important. In addition, aging mechanisms result in field failures that are often caused by multiple paramùetric deviations. In this paper we will consider the estimation of analogue test metrics under the presence of multiple parametric deviations (or process deviations) and under the presence faults.