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Towards Design And Validation Of Mixed-Technology SOCs

Auteur(s) : S. Mir, B. Charlot, G. Nicolescu, P. Coste, F. Parrain, N.-E. Zergainoh, B. Courtois, A. A. Jerraya, M. Rencz

ISRN: TIMA-RR--00/01-1--FR

This paper illustrates an approach to design and validation of het­ erogeneous systems. The emphasis is placed on devices which in­ corporate MEMS parts in either a single mixed­technology (CMOS + micromachining) SOC device, or alternatively as a hybrid sys­ tem with the MEMS part in a separate chip. The design flow is general, and it is illustrated for the case of applications embed­ ding CMOS sensors. In particular, applications based on finger­ print recognition are considered since a rich variety of sensors and data processing algorithms can be considered. A high level multi­ language/multi­engine approach is used for system specification and co­simulation. This also allows for an initial high­level ar­ chitecture exploration, according to performance and cost require­ ments imposed by the target application. Thermal simulation of the overall device, including packaging, is also considered since this can have a significant impact in sensor performance. From the selected system specification, the actual architecture is finally gen­ erated via a multi­language co­design approach which can result in both hardware and software parts. The hardware parts are com­ posed of available IP cores. For the case of a single chip implemen­ tation, the most important issue of embedded­core­based testing is briefly considered, and current techniques are adapted for testing the embedded cores in the SOC devices discussed