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On-line monitoring of properties built on regular expressions sequences

Auteur(s) : K. Morin-Allory, D. Borrione

Doc. Source: Advances in Design and Specification Languages for Embedded Systems (Selected Contributions from FDL'06)

Publisher : Springer

Pages : 197-207

Doi : doi 10.1007/978-1-4020-6149-3_12

We present an original method for generating monitors that capture sequence of events specified by logical and temporal properties under the form of assertions in declarative form written either in PSL or in SVA. The method includes an elementary monitor, a library of primitive connectors, a technique to interconnect them, and tokens either monochrome or polychrome. This results in a synthesizable digital module that can be properly connected to a digital system under verification. The complexity of the generation is proportional to the size of the sequence expression.