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Scheduling and timing analysis of HW/SW on-chip communication in MP SoC design

Auteur(s) : Y. Cho, G. Lee, K. Choi, S. Yoo, N.-E. Zergainoh

Doc. Source: Embedded Software for SoC

Publisher : Kluwer Academic Publishers

Pages : 125-136

Doi : hal-00016129

On-chip communication design includes designing software parts (operating system, device drivers, interrupt service routines, etc.) as well as hardware parts (on-chip communication network, communication interfaces of processor/IP/memory, etc.). For an efficient exploration of its design space, we need fast scheduling and timing analysis. In this work, we tackle two problems. One is to incorporate the dynamic behavior of software (interrupt processing and context switching) into on-chip-communication scheduing. The other is to reduce on-chip data storage required for on-chip communication, by making different communications to share a physical communication buffer. To solve the problems, we present both integer linear programming formulation and heuristic algorithm.