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On Software Simulation for MPSoC. A Modeling Approach for Functional Validation and Performance Estimation

Auteur(s) : F. Pétrot, P. Gerin, M.M. Hamayun

Doc. Source: Design Technology for Heterogeneous Embedded Systems

Publisher : Springer

Pages : 91-114

Doi : DOI/ 10.1007/978-94-007-1125-9_5

The performance estimation of applications running on Multi-Processor System-On-Chip (MPSoC) is required to perform software and hardware design choices and design validations. As cycle accurate simulation is very time consuming, and may have a level of accuracy that is not always needed, simulation at higher levels of abstraction is recognized as a way to perform early validation of software. Although even very abstract executable models provide interesting functional validation capabilities, they quickly become unsuitable when timing becomes an issue. Several approaches have been advocated for fast hardware/software system simulation. Many rely on the use of instruction set simulators, others simply wrap the thread code in SystemC hardware modules. Recently, native simulation, i.e. direct execution on the host without wrapping into a SystemC hardware module, has been introduced as yet another solution. This chapter briefly reviews the above mentioned approaches and focuses on native simulation. Native simulation is a promising solution to fast and accurate simulation of software that can be linked with state of the art abstract hardware simulators for both functional and temporal hardware/software system validation.