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Design of new optimized architecture processor for DWT

Auteur(s) : C. Souani, M. Atri, M. Abid, K. Torki, R. Tourki

Journal : Real Time Imaging

Volume : 6

Issue : 4

Pages : 297-312

Doi : 10.1006/rtim.1999.0178

This paper presents a VLSI implementation of One Dimensional Direct Discrete Wavelet transform (1-D DWT). The DDWT can be viewed as a multi-resolution decomposition of a signal. This means that it decomposes a signal into its components in different frequency bands (octave bands). We propose a new architecture using parallel filters. We consider the implementation of 1-D three levels DWT. The proposed architecture is simple and offers 16-bit precision on input and output data. It is constituted of three basic units: one register bank, four filters, and a control unit. The filters are of different lengths and with new coefficients derived from Daubechies filter coefficients. The designed processor architecture requires no interface circuitry for interconnection to a standard communication bus. The architecture can compute DWT at a data rate of 12x10/sup 6/ samples/s corresponding to a typical clock speed of 12 MHz. The architecture is simulated at the gate level in VLSI