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Reduced-code static linearity test of split-capacitor SAR ADCs using an embedded incremental Sigma-Delta converter

Auteur(s) : R. Silveira Feitoza, M. Barragan, D. Dzahini, S. Mir

Journal : IEEE Transactions on Device and Materials Reliability

Volume : 19

Issue : 1

Pages : 37-45

Doi : 10.1109/TDMR.2019.2891298

Reduced-code techniques for ADC static linearity test have the potential to drastically reduce the number of necessary measurements for a complete static linearity characterization. These techniques take advantage of the repetitive operation of certain families of converters such as pipelines, SARs, cyclic, etc. In this paper we present a novel reduced-code technique for the static linearity test of split-capacitor SAR ADCs based on the on-chip generation and measurement of the major carrier transitions of the input DAC of the converter. The proposed test method does not require a test stimulus, and we show that the necessary measurements can be easily extracted by reconfiguring portions of the SAR into a low-resolution Incremental Sigma-Delta converter. The proposed technique is validated with both behavioral and electrical simulations of a 10-bit SAR ADC in a 65 nm CMOS technology.