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Loop aware CFG matching strategy for accurate performance estimation in IR-level native simulation

Auteur(s) : O. Matoussi, F. Pétrot

Journal : Integration, the VLSI Journal

Doi : j.vlsi.2018.02.001

Native simulation is a promising virtual prototyping candidate to accelerate design space exploration of hardware/software systems, early software developments and functional verification. However, it originally fails to provide non-functional information needed for software performance estimation. To add this capability, the general approach is to extract performance metrics from target binary code and back-annotate it in the high-level code from which the binary was generated. However, due to compiler optimizations, the high-level code and the binary code usually have different structures which makes software annotation a complex task. This work proposes a loop-based mapping scheme that reflects optimizations from the binary to the high-level IR for the purpose of precisely placing performance annotations in the software and yielding accurate performance estimates. Experiments on instruction count show in average around 2% of error while conserving a considerable speedup compared to instruction set simulation.