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Reducing Rollback Cost in VLSI Circuits to Improve Fault Tolerance

Auteur(s) : T. Bonnoit, N.-E. Zergainoh, M. Nicolaidis

Journal : Transactions on Very Large Scale Integration (VLSI) Systems

Volume : 26

Issue : 8

Pages : 1438-1451

Doi : 10.1109/TVLSI.2018.2818021

In nanometer technologies, circuits are more and more sensitive to various kinds of perturbations. Alpha particles and atmospheric neutrons induce single-event upsets, affecting memory cells, latches, and flip-flops. They also induce single-event transients, initiated in the combinational logic and captured by the latches and flip-flops associated with the outputs of this logic. In the past, the major efforts were related on memories. However, as the whole situation is getting worse, solutions that protect the entire design are mandatory. Solutions for detecting the error in logic functions already exist, but there are only few solutions allowing the correction, leading to a lot of hardware overhead in nonprocessor design. In this paper, we present a novel technique that includes several hardware architectures and an algorithm for their implementations, which reduces the cost of rollback in any kinds of circuit.