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Dynamic Binary Translation of VLIW Codes on Scalar Architectures

Auteur(s) : L. Michel, F. Pétrot

Journal : IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volume : 36

Issue : 5

Pages : 789-800

Doi : 10.1109/TCAD.2016.2604294

Many of the recently announced integrated manycore architectures targeting specific applications embed several, if not many, very long instruction word (VLIW) processors. To start developing software while the hardware is still being designed, virtual prototypes of the full system are commonly used. Fast processor simulation is thus a requirement. To that aim, this paper introduces a strategy to perform dynamic binary translation (DBT) of VLIW codes on scalar architectures. We propose a high level simulation algorithm which takes into account VLIW oddities, such as explicit instruction parallelism, instructions with non unit register update latency, and delayed slots in branches. We present the implementation details of this algorithm within a DBT environment, as it raises many corner cases that are irrelevant in scalar DBT. Our experiments confirm that our solution is functionally correct, and show speedups of 1 and 2 orders of magnitude compared to raw instruction interpretation, even though no optimizations were performed on the code during and after translation.