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A 65nm CMOS Ramp Generator Design and its Application Towards a BIST Implementation of the Reduced-Code Static Linearity Test Technique for Pipeline ADCs

Auteur(s) : G. Renaud, M. Barragan, A. Laraba, H. Stratigopoulos, S. Mir, H. Le Gall, H. Naudet

Journal : Journal of Electronic Testing: Theory and Applications

Volume : 32

Issue : 4

Pages : 407-421

Doi : 10.1007/s10836-016-5599-8

This work presents an efficient on-chip ramp generator targeting to facilitate the deployment of Built-In Self-Test (BIST) techniques for ADC static linearity char- acterization. The proposed ramp generator is based on a fully-differential switched-capacitor integrator that is con- veniently modified to produce a very small integration gain, such that the ramp step size is a small fraction of the LSB of the target ADC. The proposed ramp generator is employed in a servo-loop configuration to implement a BIST ver- sion of the reduced-code linearity test technique for pipeline ADCs, which drastically reduces the volume of test data and, thereby, the test time, as compared to the standard test based on a histogram. The demonstration of the pipeline ADC BIST is carried out based on a mixture of transistor- level and behavioral-level simulations that employ actual production test data.