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Reduced code linearity testing of pipeline ADCs

Auteur(s) : A. Laraba, H. Stratigopoulos, S. Mir, H. Naudet, G. Bret

Journal : IEEE Design and Test of Computers

Volume : 30

Issue : 6

Pages : 80-88

Doi : 10.1109/MDAT.2013.2267957

Pipeline analog-to-digital converters have a repetitive structure, which allows analyzing their static performances by targeting only a small subset of codes. This reduced code testing is an attractive low-cost alternative to the standard techniques based on complete histograms. To guarantee accurate results, the target codes must to be carefully selected, and their measured widths must be appropriately mapped to the unmeasured widths of the remaining codes. The authors present a selection and mapping technique that is based on digital monitoring. Experimental data are provided for an 11-bit, 2.5-bit/stage, 55-nm pipeline analog-to-digital converter.