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Test Metrics Model for Analog Test Development

Auteur(s) : H. Stratigopoulos

Journal : IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volume : 31

Issue : 7

Pages : 1116 - 1128

Doi : 10.1109/TCAD.2012.2185931

The trend nowadays is to integrate more and more functionalities into a single chip. This, however, has serious implications in the testing cost. Especially for the analog circuits, the testing cost tends to be very high, despite the fact they occupy a small fraction of the area of the chip. Therefore, to reduce this cost, there is a high interest to replace the most demanding tests by alternative measurements. However, such replacement may inadvertently result in accepting faulty chips or rejecting functional chips. In this paper, we present a method for estimating such test metrics in the general scenario where a single test is replaced by a single measurement. The method is based on the extreme value theory and the statistical blockade algorithm. It can be readily applied during the test development phase to obtain estimates of the test metrics and corresponding confidence intervals with parts-per-million precision. For this purpose, the method requires a small number of selective simulations that we can afford to run in practice.