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Lightweight Transactional Memory systems for NoCs based architectures: Design, implementation and comparison of two policies

Auteur(s) : Q. Meunier, F. Pétrot

Journal : Journal of Parallel and Distributed Computing (JPDC)

Volume : 70

Issue : 10

Pages : 1024-1041

Doi : 10.1016/j.jpdc.2010.02.007

Hardware Transactional Memory (HTM) is an attractive design concept which simplifies parallel programming by shifting the problem of correct synchronization between threads to the underlying hardware memory system. There has recently been much work dealing with Hardware Transactional Memory systems, but to the best of our knowledge, all assume a write-back cache coherence protocol. As no existing HTM system is based on a write-through coherence protocol, we propose the design and implementation of an original Transactional Memory system based on a Write-Through Invalidate directory based cache coherence protocol, and we perform the comparison of this system with a more common write-back MESI (Modified Exclusive Shared Invalid) based HTM system. The comparison is done on an architecture with two possible memory repartitions, either centralized or distributed, at the cycle-accurate level. Additionally, our work takes into account the difficulties related to on-chip communication using network like interconnects, in order to be able to target the embedded domain. We compare the execution performances of both HTM systems on two micro-kernels and on a subset of the SPLASH-2 benchmarks. Results show that the coherence protocol has an impact on the execution times, but that no solution outperforms the other. However, the write-back has overall slightly better results, especially when the memory is not distributed.