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Validating Assertion Language Rewrite Rules and Semantics With Automated Theorem Provers

Auteur(s) : K. Morin-Allory, M. Boulé, D. Borrione, Z. Zilic

Journal : IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volume : 29

Issue : 9

Pages : 1436 - 1448

Doi : 10.1109/TCAD.2010.2049150

Modern assertion languages such as property specification language (PSL) and SystemVerilog assertions include many language constructs. By far, the most economical way to process the full languages in automated tools is to rewrite the majority of operators to a small set of base cases, which are then processed in an efficient way. Since recent rewrite attempts in the literature have shown that the rules could be quite involved, sometimes counterintuitive, and that they can make a significant difference in the complexity of interpreting assertions, ensuring that the rewrite rules are correct is a major contribution toward ensuring that the tools are correct, and even that the semantics of the assertion languages are well founded. This paper outlines the methodology for computer-assisted proofs of several publicly known rewrite rules for PSL properties. We first present the ways to express the PSL syntax and semantics in the prototype verification system (PVS) theorem prover, and then prove or disprove the correctness of over 50 rewrite rules published without proofs in various sources in the literature. In doing so, we also demonstrate how to circumvent known issues with PSL semantics regarding the ${ssr never}$ and ${ssr eventually}!$ operators, and offer our proposals on assertion language semantics.