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Synthesis of property monitors for online fault detection

Auteur(s) : K. Morin-Allory, E. Gascard, D. Borrione

Journal : Journal of Circuits, Systems, and Computers (JCSC)

Volume : 16

Issue : 6

Pages : 943 - 960

Doi : 10.1142/S0218126607004088

An original method for generating components that capture the occurrence of events is proposed, and logical and temporal properties of hardware/software embedded systems are monitored. The properties are written in PSL, under the form of assertions in declarative form. The method includes the construction of a library of primitive digital components for the PSL temporal and sequence operators. These building blocks are interconnected to construct complex properties, resulting in a synthesizable digital module that can be properly linked to the digital system under scrutiny.