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Gradual Refinement for Application Specific MPSoC Design from Simulink Model to RTL Implementation

Auteur(s) : K. Huang, X. Yan, Sang-Il Han, Soo-Ik Chae, A. A. Jerraya, K. Popovici, X. Guérin, L. Brisolara, L. Carro

Journal : Journal of Zhejiang University SCIENCE A (JZUS-A)

Volume : 10, Number 2, February

Pages : 151-164

Doi : 10.1631/jzus.A0820085

The application-specific multiprocessor system-on-chip (MPSoC) architecture is becoming an attractive solution to deal with increasingly complex embedded applications, which require both high performance and flexible programmability. As an effective method for MPSoC development, we present a gradual refinement flow starting from a high-level Simulink model to a synthesizable and executable hardware and software specification. The proposed methodology consists of five different abstract levels: Simulink combined algorithm and architecture model (CAAM), virtual architecture (VA), transactional accurate archi¬tecture (TA), virtual prototype (VP) and field-programmable gate array (FPGA) emulation. Experimental results of Motion-JPEG and H.264 show that the proposed gradual refinement flow can generate various MPSoC architectures from an original Simulink model, allowing processor, communication and tasks design space exploration