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Multisynchronous and Fully Asynchronous NoCs for GALS Architectures

Auteur(s) : H. Sheibanyrad, A. Greiner, I. Miro-Panades

Journal : IEEE Design and Test of Computers

Volume : 25

Issue : 6

Pages : 572-580

Doi : 10.1109/MDT.2008.167

Networks on chips constitute a new design paradigm for communication infrastructures in large multiprocessor SoCs. NoCs can use the GALS technique to address the difficulty of distributing a synchronous clock signal on the entire chip area. This article describes two approaches to implementing a distributed NoC in a GALS environment.