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Spurious transitions in adder circuits: analytical modelling and simulation

Auteur(s) : S.-J. Abou-Samra, B. Laurent, A. Guyot

Doc. Source: International Conference on Very Large Scale Integration (VLSI'97)

Adder architectures are presented here by an unified formalism, and analysed from the delay, complexity and power consumption points of view. An analytical model for the power consumption is derived, assuming that it is proportional to the transition density. The model is subsequently validated by simulation using a signal transition probabilities propagation tool. Finally, glitches are taken into account when transitions at the input of a cell are separated by one or more cell delays. A redundant to total power ratio is also derived.