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VCI : a VHDL-C interface generation tool for cosimulation

Auteur(s) : C. Valderrama, Ph. Le Marrec, A. A. Jerraya

Doc. Source: IEEE Second International High Level Design Validation and Test Workshop (HLDTV'97)

Publisher : IEEE

This paper deals with distributed cosimulation for heterogeneous systems prototyping. We presents a cosimulation environment who allows to handle all kinds of distributed architectures, any number of hardware or software modules, cosimulation at different abstraction levels, several cosimulation scenarios and smooth transition to the cosynthesis process. This flexibility is obtained thanks to an automatic cosimulation interface generation tool able to create the link between simulation environments. The advantages of our cosimulation methodology and more precisely the automatic cosimulation interface generation tool will be described by an example.