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Cost evaluation in the design for reuse context

Auteur(s) : I. Moussa, M. Diaz-Nava, A. A. Jerraya

Doc. Source: 2nd GI/ITG/GMM-Workshop, Reuse Techniques for VLSI Design

This paper evaluates the cost of design for reuse through the design of an Asynchronous Transfer Mode (ATM) Shaper macro. This macro block is made of 2 Million of transistors and is composed of several modules or sub-systems. Some of these blocks are designed in order to be reused in orther applications. This study shows that the modules designed for reuse requires up to 2.5 time more than those designed to be specific in our Shaper. The extra cost is mainly related to the time spent in three main areas : extensive analysis of the block and its potential application domains, the development of a more robust and complete test bench environment, and the preparation of a good documentation. Furthermore, we will show that this overhead cost is recovered if the macro-block is reused several times. However in some cases, we can reach the objectives of time-to-market constraints from the first reuse time.