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Total dose and Single Event Effects (SEE) in a 0.25 µm CMOS technology

Auteur(s) : G.F. Marchioro, P. Moreira, E. Noah, W. Snoeys, T. Calin, J. Cosculluela, R. Velazco, M. Nicolaidis, A. Giraldo, F. Faccio, G. Anelli, M. Campbell, M. Delmastro, P. Jarron, K. Kouklinas

Doc. Source: Fourth Workshop on electronics for LHC experiments (LEB'98)

Individual transistors, resistors and shift registers have been designed using radiation tolerant layout practices in a commercial quarter micron process. A modelling effort has led to a satisfactory formulation for the effective aspect ratio of the enclosed transistors used in these layout practices. All devices have been tested up to a total dose of 30Mrad(SiO2). The threshold voltage shift after irradiation and annealing was about +45mV for NMOS and -55mV for PMOS transistors, no leakage current appeared, and the mobility degradation was below 6%. The value of resistors increased by less than 10%. Noise measurements made on transistors with W=2mm and L varying between 0.36 and 0.64µm revealed a corner noise frequency of about 200kHz for the NMOS and 12Hz for the PMOS. Irradiation up to 30Mrad(SiO2) did not significantly affect the noise performance. The shift registers continuously operated at 1.25MHz during the irradiation, and no error was detected in the pattern propagation. No functional degradation was observed. An irradiation with a heavy ion beam was made on the shift registers to study their sensitivity to Single Event Effects (SEE). No single Event Latch-up (SEL) was observed up to a LET of 89 MeVcm2mg-1. The register designed using dynamic logic, with a threshold LET lower than 3.2 MeVcm2mg-1, proved to be considerably more sensitive to Single Event Upset (SEU) than its static logic counterpart, which had a threshold LET of about 15 MeVcm2mg-1. A novel SEU-tolerant design was demonstrated to be extremely effective as storage cell.