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Scheduling and timing analysis of HW/SW on-chip communication in MP SoC design

Auteur(s) : Y. Cho, K. Choi, N.-E. Zergainoh, G. Lee, S. Yoo

Doc. Source: Design, Automation and Test in Europe (DATE'03)

Publisher : IEEE

On-chip communication design includes designing software (SW) parts (operating system, device drivers, interrupt service routines, etc.) as well as hardware (HW) parts (on-chip communication network, communication interfaces of processor/IP/memory, on-chip memory, etc.). For an efficient exploration of its design space, we need fast scheduling and timing analysis. In this work, we tackle two problems (one for SW and the other for HW) in on-chip communication design. One is to incorporate the dynamic behavior of SW (interrupt processing and context switching) into on-chip communication scheduling. The other is to reduce on-chip data storage required for on-chip communication, by sharing physical communication buffers with different communication transactions. To solve the problems, we present both ILP (integer linear programming) formulation and heuristic algorithm, which enable the designer to perform efficient onchip communication scheduling and obtain accurate timing information. Experimental results show the effectiveness of our work.