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Personalization of the architecture produced by High Level Synthesis for the RT Level

Auteur(s) : R. Pistorius, V. P. Vijayaraghavan, P. Kission, A. A. Jerraya

Doc. Source: International Workshop on Logic and Architecture Synthesis (IWLAS'96)

In this paper we introduce an extension of behavioral synthesis to the configuration of an entire system by regrouping synthesizable and nonsynthesizable blocks and by using the concepts of architecture personalization. This renders the resulting architecture at the register transfer level more flexible. The main issue of the architecture personalization is the generation of complete system descriptions compatible with existing RTL simulation and synthesis tools. The personalization scheme presented has been integrated within the Amical behavioral synthesis environment and has been applied successfully to several examples.