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Correct reuse of complex design units during high level synthesis: verification issues

Auteur(s) : J. Dusina, D. Borrione, A. A. Jerraya

Doc. Source: 1st IEEE International High Level Design Validation and Test Workshop (HLDVT'96)

Publisher : IEEE

The paper proposes a new model for verification and high level synthesis (re)using complex units like co-processors. The model is called FSMC (FSM with Co-processors) and is an extension of the FSMD model (FSM with Data path). The verification method is based on model checking. It permits to analyze the properties and consistency of the whole system and, particularly, the correct (re)use of design blocks.