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Systematic design flow for fast hardware/software prototype generation from bus functional model for MPSoC

Auteur(s) : I. Petkov, P. Amblard, M. Hristov, A. A. Jerraya

Doc. Source: 16th International Workshop on Rapid System Prototyping (RSP'05)

Publisher : IEEE

Pages : 218-224

Doi : 10.1109/RSP.2005.48

System design at higher level of abstraction is a promising technique to deal with the increasing complexity of the modern embedded systems. Current MPSoC are designed at register transfer level. The bus functional model is a higher level of abstraction that allows the integration of heterogeneous hardware, software components and sophisticated communication interconnects to adapt different description models. This system abstraction model makes it possible to accelerate the simulation but ignores the accuracy of the developed circuit. This paper studies an example of system design transformation from a high level of abstraction to the physical prototype of a multiprocessor system on chip. With this work we propose a systematic and efficient design flow for system on chip integration from a bus functional level of abstraction towards physical prototyping of embedded systems. The flow is applied to accelerate an MPSoC example design.