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A built-in IDDQ testing circuit

Auteur(s) : S. Matakias, Y. Tsiatouhas, A. Arapoyanni, Th. Haniotakis, G. Prenat, S. Mir

Doc. Source: 31st European Solid-State Circuits Conference (ESSCIRC'05)

Publisher : IEEE

Pages : 471-474

Doi : 10.1109/ESSCIR.2005.1541662

Although I/sub DDQ/ testing has become a widely accepted defect detection technique for CMOS ICs, its effectiveness in very deep submicron technologies is threatened by the increased transistor leakage current. In this paper, a built-in I/sub DDQ/ testing circuit is presented, that aims to extend the viability of I/sub DDQ/ testing in future technologies and first experimental results are discussed.