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VHDL based design methodology for hierarchy and component re-use

Auteur(s) : P. Kission, Hong Ding, A. A. Jerraya

Doc. Source: European Design Automation Conference with EURO-VHDL (EURO-DAC'95)

Publisher : IEEE

Pages : 470-475

Doi : 10.1109/EURDAC.1995.527446

This paper presents a VHDL specification methodology aimed to extend structured design methodologies to the behavioral level. The goal is to develop VHDL modeling strategies in order to master the design and analysis of large and complex systems. Structured design methodologies are combined with AMICAL, a VHDL based behavioral synthesis tool, in order to allow hierarchical design and component re-use.