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Digital test of a ΣΔ modulator in a mixed-signal BIST architecture

Auteur(s) : L. Rolindez, S. Mir, G. Prenat

Doc. Source: SPIE Microtechnologies for the New Millennium, VLSI circuits and systems II

Publisher : SPIE

Pages : 502-512

Doi : 10.1117/12.607615

Oversampling Sigma-Delta modulators are commonly used in the design of high-resolution Analogue-to-Digital Converters (ADCs). The test of these ΣΔ modulators is a difficult and expensive task due to the need for the generation of a high-precision analogue test signal and the necessity of complex digital resources for the test response analysis. These problems can be overcome with the integration of the test in the chip by means of Built-In Self-Test (BIST) approaches. In this paper we present a BIST technique for high-precision ΣΔ modulators, by incorporating on-chip test signal generation and on-chip test response analysis capabilities. The approach, mostly digital, is based on the application of a binary stream as test stimulus and the re-use of the digital decimation filter present in a ΣΔ ADC for the test response analysis. The binary stimulus, which encodes a sinusoidal signal, is chosen to have a very high quality in the bandwidth of interest of the modulator. For the analysis of the test response, a high-precision sinusoidal signal is necessary as reference. This reference signal can be obtained from the same binary stimulus, by passing it directly to the digital decimation filter existing in the converter. Test response and sinusoidal reference signal are both compared by means of a sine-wave curve-fitting algorithm in order to obtain a measure of the SNDR (Signal-to-Noise-plus-Distortion Ratio). Simulation results show that this technique is capable of detecting the SNDR degradations caused by non-idealities in the modulator used in a 16-bit audio ΣΔ ADC architecture.