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Flexible MPSoC platform with fast interconnect exploration for optimal system performance for a specific application

Auteur(s) : F. Dumitrascu, I. Bacivarov, L. Pieralisi, M. Bonaciu, A. A. Jerraya

Doc. Source: Design Automation and Test Conference in Europe (DATE'06)

Publisher : IEEE

Pages : 166 - 171

One of the key elements in Multi-Processor Systems-on-Chip (MPSoC) design is to select the optimal on-chip interconnect architecture, in order to maximize the overall system performance. This paper proposes a flexible MPSoC platform, designed for a target application, which allows customizing the interconnect by selecting various architectures. It allows fast building of executable models from architecture specifications and performance evaluation using the cycle-accurate cosimulation. We experimented a DivX encoder application with three different interconnects: DMS (Distributed Memory Server), AMBA bus and Octagon Network-on-Chip (NoC). The simulation results relative to performance metrics such as, average latency, throughput and execution time allowed to compare these different interconnect architectures, to verify the application real-time constraints and to propose further optimizations.