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Analysis of different protocol description styles in VHDL for high-level synthesis

Auteur(s) : L. Pirmez, A. Pedroza, M. Rahmouni, A. Mesquita, P. Kission, A. A. Jerraya

Doc. Source: European Design Automation Conference (EURO DAC'96) with EURO VHDL'96 and Exhibition

Publisher : IEEE

Pages : 490-495

Doi : 10.1109/EURDAC.1996.558248

When synthesizing control-flow dominated descriptions based on VHDL, different styles of semantically equivalent descriptions may differ significantly in quality. This paper discusses the effect of the input description on High-Level Synthesis when using VBDL. In order to show this effect, a high speed protocol based on the ISO reference protocol Abracadabra is used. Five VHDL descriptions styles of the same protocol have been synthesized using AMICAL, a VHDL based behavioral synthesis tool. Discussions of the different results leads to a VHDL based methodology for protocol modelling in order to produce efficient designs.