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A recursive high level synthesis system

Auteur(s) : J.C. Wang, M.Y. Teruya, J.V.V. Neto, M. Strum, A. A. Jerraya

Doc. Source: 5th International Conference on VLSI and CAD (ICVC'97)

Publisher : Samsung Electron, Kyungki do, South Korea

Pages : 412-414

A hierarchical high level synthesis (HHLS) system, such as AMICAL, allows the obtaining of an architecture for a circuit from its behavioral description, written as a hierarchy of procedures and function calls, proper of large circuits. When specific modules are synthesized and reused as basic hardware modules in another HLS session, the resulting architecture may be inefficient due to operations overlap among the allocated hardware modules. This paper presents the structure of a CAD system that treats this problem by generating new hardware modules through a set of transformations to be applied to existing modules in an original library. We call the procedure of generating and reusing these new modules recursive high level synthesis (RHLS) which leads to a more efficient architecture. We propose a cost function that evaluates the quality of each architecture, taking into account area and time, and we present criteria to select the most promising transformation. The methodology is applied to a motor controller example (PID), showing its feasibility.