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VHDL generation from SDL specifications

Auteur(s) : J.- M. Daveau, G.F. Marchioro, C. Valderrama, A. A. Jerraya

Doc. Source: IFIP TC10 WG10.5 International Conference on Computer Hardware Description Languages and their Applications (CHDL'97)

Publisher : Chapman & Hall, London, UK

Pages : 182-201

The aim of this paper is to present an approach that allows the generation of VHDL from system level specifications in SDL. Our approach overcomes the main known problem encountered by previous work which is the communication between different processes. We allow SDL communication to be translated into VHDL for synthesis. This is made possible by the use of an intermediate form that supports a powerful communication model which enables the representation, in a synthesis-oriented manner, of most communication schemes. This intermediate form allows the refinement of the system in order to obtain the desired solution. The main refinement step, called communication synthesis, is aimed at fixing the protocol and the interface used by the different processes to communicate. The refined specification is translated into VHDL for synthesis using existing CAD tools. We illustrate the feasibility of our approach through two SDL to VHDL translation examples.