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Modeling Novel Non-JTAG IEEE 1687-Like Architectures

Auteur(s) : M. Laisne, A. Crouch, M. Portolan, M. Keim, H.M Von Staudt, M. Abdalwahab, B. Van Treuren, J. Rearick

Doc. Source: International Test Conference (ITC 2020)

Many modern devices have a very limited number of digital pins, yet they are often quite complicated internally. Such These ICs can’t afford the luxury of a traditional JTAG TAP controller and the associated 4 or 5 extra pins. Nonetheless, these devices often contain significant digital and analog content. This complexity makes testing very challenging. Moreover, IP-based design might often results in having an instrument buried deep inside a device, whose the access of which requires transitioning through multiple interfaces and controllers. This is exactly the situation DfT and test engineers face when designing and implementing tests for embedded IP. Techniques proposed for IEEE P1687.1 enable an automated mechanism for retargeting tests through a variety of non-TAP interfaces. This makes these products ideal candidates for IJTAG and IJTAG.1 test strategies. In this paper, we focus on demonstrating how on-chip test functions and IP can be successfully controlled and observed through non-TAP interfaces by controlling data flow using RVF (Relocatable Vector Format) and callbacks. This unique and novel approach ensures tool interoperability and allows tools to view model interfaces in the same way, without requiring special descriptions for each one. The paper proposes an automated tool flow for retargeting the tests and provides example implementations on several specialized designs including I2C, IEEE 1149.7, TPSP (2 pin Serial Port)an In-System TAP, IEEE 1149.7-like interface, and a security block