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New Perspectives on Core In-field Path Delay Test

Auteur(s) : L. Anghel, R. Cantoro, D. Foti, M. Portolan, S. Sartoni, M. Sonza Reorda

Doc. Source: International Test Conference (ITC 2020)

With the advance in silicon technology, the increasingly strict timing requirements and the overwhelming density of recent electronic devices, delay faults are gaining a more relevant position. This kind of faults can be induced by several causes, like defects in the manufacturing processes, process variations as well as aging, workload, cross-talk and many others. While transition delay faults are commonly targeted in industrial practice, path delay faults are less frequently addressed. Path Delay fault test currently exploits DfT-based techniques, mainly relying on scan chains, widely supported by commercial tools. However, functional testing may be a desirable choice in this context because it allows to catch faults at-speed with no hardware overhead and it can be used both for end-of- manufacturing tests and for in-field test. The purpose of this article is to compare the results that can be achieved with both approaches. This work is based on an open-source RISCV-based processor core as benchmark device. Gathered results show that there is no correlation between stuck-at and path delay fault coverage, and provide guidelines for developing more effective functional test.