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Accurate MPSoC prototyping platform and methodology for the studying of the Linux synchronization barrier slowdown issues

Auteur(s) : M. France-Pillois, J. Martin, F. Rousseau

Doc. Source: International Symposium on Rapid System Prototyping (RSP'2018)

Publisher : IEEE

Pages : 56-62

The benefit expected from the hardware parallelism offered by Multi-Processor System on Chips (MPSoCs) is determined by the ability to design high-performance synchronization mechanisms. The complexity of modern MPSoCs does not allow anymore to design an optimized software application without confront it with the hardware platform restrictions. In this paper, we propose a methodology to study the impact of hardware contention in the synchronization barrier mechanism running on a shared memory clustered MPSoC. Taking advantage of this new observation methodology based on emulation, we identify hardware module restrictions and Linux kernel suboptimal services. We show how the introduction of delays in the thread awakening process improves the overall synchronization mechanism. Then we detail how a combined Hardware/Software optimization for the passive wait of the synchronization barrier provides a large gain: about 60% for 64 threads running on a 64-core architecture.