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Laser Fault Injection at the CMOS 28 nm Technology Node: an Analysis of the Fault Model

Auteur(s) : J.M. Dutertre, V. Beroulle, P. Candelier, S. De Castro, L.-B. Faber, M.-L. Flottes, P. Gendrier, D. Hély, R. Leveugle, P. Maistri, G. Di Natale, A. Papadimitriou, B. Rouzeyre

Doc. Source: Fourteenth Workshop on Fault Diagnosis and Tolerance in Cryptography (FDTC'2018)

Publisher : IEEE Circuits and Systems society

S. Skorobogatov and R. Anderson identified laser illumination as an effective technique to conduct fault attacks in 2002. In these early days of laser-induced fault injection, it was proven to be possible to inject single-bit faults into integrated circuits. This corresponds to the more restrictive fault model found in the fault attack bibliography. The target area under laser illumination (a few micrometers, down to ~1µm) broadly matched that of a single transistor. It was consistent with a singlebit fault model. However, since then the technology of secure devices has evolved. In current circuits even the smallest laser spots may illuminate several logic cells. This raises the question of the validity of the single-bit fault model: does it still hold? In this work, we report an assessment of its validity through experimental results obtained from circuits designed at the 28nm CMOS technology node. We also describe the main properties of the corresponding fault model obtained from both static and dynamic experiments.