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A mapping approach between IR and binary CFGs dealing with aggressive compiler optimizations for performance estimation

Auteur(s) : O. Matoussi, F. Pétrot

Doc. Source: 23rd Asia and South Pacific Design Automation Conference (ASPDAC'2018)

Publisher : IEEE

Pages : 452-457

Doi : 10.1109/ASPDAC.2018.8297365

In this work, we define a mapping approach between the compiler intermediate representation and the binary control flow graph for the purpose of performance estimation in native simulation. Our approach handles aggressive compiler optimizations such as loop unrolling without having to introduce any modification to the compiler. Our mapping approach experimentally leads to a good accuracy (0.59% error) while keeping a 25x speedup for native simulation compared to instruction set simulation.