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Linux Synchronization Barrier on MPSoC: Hardware/Software Accurate Study and Optimization

Auteur(s) : M. France-Pillois, J. Martin, F. Rousseau

Doc. Source: International Conference on Application-Specific Systems, Architectures and Processors (ASAP 2018)

Publisher : Springer

Pages : 1-4

Doi : doi.org/10.1109/ASAP.2018.8445120

Providing high-performance synchronization mechanisms is a key issue to benefit from hardware parallelism offered by MPSoCs. In this paper, we focus our study on the synchronization barrier mechanism and the impact of hardware contention in shared memory clustered MPSoC. Taking advantage of a new observation methodology based on emulation, we identify Linux kernel sub-optimal services. We show how the introduction of delays in the thread awakening process improves the overall synchronization mechanism resulting in an optimization of the synchronization barrier in passive wait mode providing a large gain: 67% for 64 threads running on a 64-core architecture.