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HLS Design of a Hardware Accelerator for Homomorphic Encryption

Auteur(s) : A. Mkhinini, P. Maistri, R. Leveugle, R. Tourki

Doc. Source: IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS 2017)

Publisher : IEEE

Doi : 10.1109/DDECS.2017.7934578

Modular polynomial multiplication is the most computationally intensive operation in many homomorphic encryption schemes. In order to accelerate homomorphic computations, we propose a software/hardware (SW/HW) co-designed accelerator integrating fast software algorithms with a configurable hardware polynomial multiplier. The hardware accelerator is implemented through a High-Level Synthesis (HLS) flow. We show that our approach is highly flexible, since the same generic high-level description can be configured and re-used to generate a new design with different parameters and very large sizes in negligible time. We show that flexibility does not preclude efficiency: the proposed solution is competitive in comparison with hand-made designs and can provide good performance at low cost.