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Analysis of an efficient on-chip servo-loop technique for reduced-code static linearity test of pipeline ADCs

Auteur(s) : G. Renaud, M. Margalef-Rovira, M. Barragan, S. Mir

Doc. Source: VLSI Test Symposium (VTS 2017)

Publisher : IEEE

Doi : 10.1109/VTS.2017.7928951

This work presents an efficient modification of the classical servo-loop static test setup aimed at the on-chip imple- mentation of reduced-code static linearity test techniques. The proposed modified servo-loop provides a direct measurement of the width of a given ADC code without the need of an integrated voltmeter. The proposed measurement strategy is based on using a controlled step-wise ramp stimulus generator for exciting the ADC under test in such a way that the measurement of a code width can be determined in the digital domain by simply counting the number of ramp steps between two consecutive ADC output transitions. Moreover, the ability of the proposed servo-loop to target a given ADC code makes it very suitable for implementing advanced reduced-code static test techniques. This work analyses the performance limits of the proposed discrete-time servo-loop technique and explores its application to reduced-code linearity testing of pipeline ADCs.