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A survey of NoC evaluation platforms on FPGAs

Auteur(s) : O. Alcantara, W. Costa, V. Fresse, F. Rousseau

Doc. Source: International Conference on Field-Programmable Technology

Publisher : IEEE

Networks-on-chip (NoCs) have become a de facto communication standard for many core systems-on-chip (SoCs). A NoC has large design space composed of several parameters such as routing algorithm, task mapping, among others. SoC designers deeply rely on automatic evaluation tools in order to deal with the complexity of NoC design. An important class of NoCs evaluation tools are the platforms based on FPGAs, which improve the evaluation time and precision when compared to other solutions. There are different architectures of FPGA- based NoC evaluation tools. Details are scattered among several papers, making a comparative analysis hard to accomplish. This paper presents a comprehensive overview of FPGA tools for NoC evaluation. Our analysis covers aspects like network architecture, traffic generation and interface to the host PC. This provides insight on the platforms and their usefulness for different NoC evaluation tasks.