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ADC techniques for optimized conversion time in CMOS image sensors

Auteur(s) : C. Pastorelli, P. Mellot, S. Mir, C. Tubert

Doc. Source: IS&T International Symposium on Electronic Imaging, Image Sensors and Imaging Systems

Pages : 268.1-268.6

For several decades, many CMOS Image Sensors (CIS) with a small pixel size have used single slope column parallel ADCs (SS-ADC). It is well known that the main drawback of this ADC is the conversion speed. This paper presents several ADC architectures which improve the speed of a SS-ADC. Different architectures are compared in terms of ADC resolution, power consumption, noise and conversion time.