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Loop aware IR-level annotation framework for performance estimation in native simulation

Auteur(s) : O. Matoussi, F. Pétrot

Doc. Source: 22nd Asia and South Pacific Design Automation Conference (ASPDAC 2017)

Publisher : IEEE

Pages : 220-225

Doi : 10.1109/ASPDAC.2017.7858323

Native simulation is an interesting virtual prototyping candidate to speed-up architecture exploration and early software developments. It however does not provide out-of-the box non-functional information needed for software performance estimation. Annotating software with information is complex as highlevel codes and binary codes have different structures due to compiler optimizations. This work proposes an annotation framework at compiler IR-level that focuses on loop structures, and reflects optimizations through a mapping scheme between the binary and the high-level IR. Experiments on instruction count show in average around 2% of error.