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Hardware Design of Error Detection Schemes for Symmetric Ciphers

Auteur(s) : P. Maistri

Doc. Source: Séminaire sécurité des systèmes électroniques embarqués

Secure hardware implementations are often used to accelerate cryptographic implementations; however, designers are well aware that cost and performance are not their only goal. Attacks exploiting side channel leakage or faulty behaviour are a serious threat that do not always require expensive equipment to be carried out, and can affect both symmetric and public-key cryptosystems. Hardware implementations must hence adopt solutions in order to make these attacks harder. In this talk we will present a few schemes aiming at detecting faulty computations in symmetric ciphers, with a particular focus on the Advanced Encryption Standard. Two countermeasures will be primarily addressed: temporal redundancy based on a double-data rate computation scheme, and a parity-based error detection code automatically generated from the RTL structure of the design. Several experimental results will be provided in order to show the validity of the proposed approaches.