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A 4x4x2 homogeneous scalable 3d network-on-chip circuit with 326mflit/s 0.66pj/b robust and fault-tolerant asynchronous 3d links

Auteur(s) : P. Vivet, Y. Thonnard, R. Lemaire, E. Beigné, Ch. Bernard, F. Darve, D. Lattard, I. Miro-Panades, Cr. Santos, F. Clermidy, S. Cheramy, F. Pétrot, E. Flamand, J. Michailos

Doc. Source: IEEE International Solid-State Circuits Conference (ISSCC'16)

Publisher : IEEE

Doi : 10.1109/ISSCC.2016.7417949

By shortening communication distance across dies, 3D technologies are a key to continued improvements in computing density. For 4G telecom baseband processing, specific computing units arranged in a regular network-on-chip (NoC) array provide power-efficient computation [1]. However, for advanced MIMO processing, more computing power is required when the number of antennas increases. This paper presents a homogeneous 3D circuit composed of regular tiles assembled using a 4x4x2 network-on-chip, using robust and fault tolerant asynchronous 3D links, providing 326MFlit/s @ 0.66pJ/b, fabricated in CMOS 65nm technology using 1980 TSVs in a Face2Back configuration.