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Early system failure prediction by using aging in situ monitors: Methodology of implementation and application results

Auteur(s) : L. Anghel, A. Benhassain, A. Sivadasan

Doc. Source: IEEE 34th VLSI Test Symposium (VTS'16)

Publisher : IEEE

Doi : 10.1109/VTS.2016.7477316

With CMOS technology scaling, it becomes more and more difficult to guarantee circuit functionality for all process, voltage, temperature (PVT) corners. Moreover, circuit wear-out degradation lead to additional temporal variations, resulting in an important increase of design margins when targeting specific reliable systems (automotive or health care embedded applications) [1]. Adding pessimistic timing margin to guarantee all operating points under worse case conditions is no more acceptable due to the huge impact on design costs, such as up to 10% increase of slack time, with an upward trend as technology moves further.