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AHLS_DESYNC: A Desynchronization Tool For High-Level Synthesis of Asynchronous Circuits

Auteur(s) : J. Simatic, R. Possamai Bastos, L. Fesquet

Doc. Source: Design, Automation and Test in Europe (DATE'16) - University Booth

Publisher : IEEE

We present a tool for the high-level synthesis (HLS) of event-driven (asynchronous) circuits. Our approach first uses an existing HLS tool, AUGH, to generate a synchronous finite state machine (FSM) and a data-path. Then, the presented tool desynchronizes solely the FSM in 5 steps: 1. Parse the FSM to build a state graph containing the control signal assignments. 2. Separate multiplexer control and register control signals by analyzing the data-path. 3. Generate an event-driven FSM netlist by mapping the state graph on a dedicated set of asynchronous controllers. 4. Synthesize the data-path thanks to a commercial synthesis tool (Design Compiler). 5. Estimate the delays in the data-path with a static timing analysis tool (PrimeTime). Insert delays in the controller accordingly. Our demonstration will exhibit two testbenches: a GCD algorithm to expose the basic concepts and a non-uniform sampling FIR filter more representative of real-life applications.